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Lattice Semiconductor
Turbo Decoder User’s Guide
Output Data Handshaking
When the decoder is ready to output data, signal rfo is asserted high after the decoder has completed the speci-
?ed number of iterations. The user can then assert signal rfno to read the decoded data, which then allows data
to be output on dout .
A synchronous reset signal, sr is available to reinitialize the Turbo Decoder in the middle of a block processing.
The current block being processed will be completely discarded during this reset. This can be done at any point of
time during the operation
Memory Buffer
The memory buffering for this IP splits into four sections. These sections are described in detail below.
Input Data/Parity Memory
The Turbo Decoder core requires a large amount of memory to store the input data block. Since data memory
requirements are large, an external memory is recommended so that on-chip memory can be used for other pur-
poses. An external memory interface is provided in the IP. A single or double buffer memory mode may be selected
depending on the available external memory at hand. Double buffer memory allows one block of data to be pro-
cessed while another block is written and read. Double buffer memory delivers better performance than the single
buffer selection by minimizing delay between the processing of each block.
Internal Memory
Some internal memory is required to implement the interleaver and other necessary functions of the Turbo
Decoder. Lattice’s Turbo Decoder requires a small amount of memory for internal purposes. For example, the
3GPP con?guration uses 4.6Kb spread over four memory blocks.
LLR Memory
After the Turbo Decoder completes the required number of iterations, the LLR memory buffer stores the ?nal LLR
values. The size of the LLR memory buffer is dependant on con?guration and block size.
Hard Decision Storage Memory
The Turbo Decoder IP core offers optional hard decision storage. When LLR memory is used as an output buffer,
the decoder cannot go onto process the next block of data until current LLR values of the previous block are com-
pletely read out. This results in an extra processing delay of B cycles (B = blocksize ). To minimize delay, output
data after hard decision can be stored in separate memory to allow the decoder to operate on a new data block if
memory can be spared.
Operational Data Flow
The following ?ow diagram describes the sequence for every block introduced into the Turbo Decoder core.
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